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FPGA可编程逻辑器件芯片XC2V8000-5FF1152I中文规格书
时间：2023-03-31 20:52:30 下载该word文档
Chapter1: VC707EvaluationBoardFeatures •Quad113:••• • MGTREFCLK0-SGMIIclock MGTREFCLK1-SMAclock Contains3GTXtransceiverswithoneeachallocatedtoSMA,SGMIIandSFPContains1unusedGTXtransceiverMGTREFCLK0-Si5324jitterattenuatorContains4GTXtransceiversforPCIe®lanes4–7MGTREFCLK1-PCIeedgeconnectorclockContains4GTXtransceiversforPCIelanes0–3 MGTREFCLK0-FMC2HPCGBTCLK1 Contains4GTXtransceiversforFMC2HPC(DP4–DP7 MGTREFCLK0-FMC2HPCGBTCLK0 Contains4GTXtransceiversforFMC2HPC(DP0–DP3 MGTREFCLK0-FMC1HPCGBTCLK1 Contains4GTXtransceiversforFMC1HPC(DP4–DP7 MGTREFCLK0-FMC1HPCGBTCLK0 Contains4GTXtransceiversforFMC1HPC(DP0–DP3 •Quad114:• • •Quad115:• • •Quad116:• • ••Quad117:• • •Quad118:• • •Quad119:• • Table1-11liststheGTXinterfaceconnectionstotheFPGA(U1. Table1-11: GTXInterfaceConnectionsforFPGAU1 FHG1761PlacementGTXE2_CHANNEL_X1Y0GTXE2_CHANNEL_X1Y1GTXE2_CHANNEL_X1Y2GTXE2_CHANNEL_X1Y3MGTREFCLK0 MGTREFCLK1 MGT_BANK_114 GTXE2_CHANNEL_X1Y4GTXE2_CHANNEL_X1Y5GTXE2_CHANNEL_X1Y6GTXE2_CHANNEL_X1Y7MGTREFCLK0 MGTREFCLK1 SMASGMIISFP+NCSGMII_CLKSMA_MGT_REFCLKPCIe7PCIe6PCIe5PCIe4Si5324 NC Connections TransceiverBank MGT_BANK_113 VC707EvaluationBoard UG885(v1.8February20,2019
FeatureDescriptions VITA57.1FMC1HPCConnector(PartiallyPopulated [Figure1-2,callout30 ] TheVC707boardimplementstwoinstancesoftheFMCHPCVITA57.1specificationconnector. ThissectiondiscussestheFMC1HPCJ35connector. Note: TheFMC1HPCJ35connectorisakeyedconnectororientedsothataplug-oncardfaces awayfromtheVC707board. TheVITA57.1FMCstandardcallsfortwoconnectordensities:ahighpincount(HPCandalowpincount(LPCimplementation.A400pin10x40positionconnectorformfactorisusedforbothversions.TheHPCversionisfullypopulatedwithall400pinspresent.TheLPCversionispartially populatedwith160pins. The10x40rowsofanFMCHPCconnectorprovidespinsforupto:•••• • 160single-endedor80differentialuser-definedsignals10GTXtransceivers2GTXclocks 4differentialclocks 159groundand15powerconnections TheVC707boardFMC1HPCconnectorJ35implementsasubsetofthemaximumsignalandclockconnectivitycapabilities:•••••• • 80differentialuser-definedpairs34LApairs(LA00-LA3324HApairs(HA00-HA2322HBpairs(HB00-HB218GTXtransceivers2GTXclocks 2differentialclocks TheFMC1HPCsignalsaredistributedacrossGTXQuads118and119.EachQuadhastheVCCOvoltageconnectedtoV ADJ. Note: TheVC707boardVADJvoltagefortheFMC1HPC(J35connectorisdeterminedbythe FMCVADJpowersequencinglogicdescribedinFMC_VADJVoltageControl . VITA57.1FMC2HPCConnector(PartiallyPopulated [Figure1-2,callout31 ] TheVC707boardimplementstwoinstancesoftheFMCHPCVITA57.1specificationconnector. ThissectiondiscussestheFMC2HPCJ37connector. Note: TheFMC2HPCJ37connectorisakeyedconnectororientedsothataplug-oncardfaces awayfromtheVC707board. TheFMCstandardcallsfortwoconnectordensities:aHighPinCount(HPCandaLowPinCount(LPCimplementation.A400pin10x40positionconnectorformfactorisusedforbothversions.TheHPCversionisfullypopulatedwithall400pinspresent.TheLPCversionispartiallypopulated with160pins. VC707EvaluationBoard UG885(v1.8February20,2019
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FPGA可编程逻辑器件芯片XC2V8000-5FF1152I中文规格书
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